View IDT72V235L20PFI_4914468.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 february 2002 idt72v205, idt72v215, idt72v225, idt72v235, idt72v245 idt and the idt logo are registered trademarks of integrated device technology, inc. syncfifo is a trademark of integrated devi ce technology, inc. commercial and industrial temperature ranges ? 2002 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-4294/3 3.3 volt cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 features: 256 x 18-bit organization array (idt72v205) 512 x 18-bit organization array (idt72v215) 1,024 x 18-bit organization array (idt72v225) 2,048 x 18-bit organization array (idt72v235) 4,096 x 18-bit organization array (idt72v245) 10 ns read/write cycle time 5v input tolerant idt standard or first word fall through timing single or double register-buffered empty and full flags easily expandable in depth and width asynchronous or coincident read and write clocks asynchronous or synchronous programmable almost-empty and almost-full flags with default settings half-full flag capability output enable puts output data bus in high-impedanc state high-performance submicron cmos technology available in a 64-lead thin quad flatpack (tqfp/stqfp) industrial temperature range (C40 c to +85 c) is available functional block diagram input register output register ram array 256 x 18, 512 x 18 1,024 x 18, 2,048 x 18 4,096 x 18 offset register flag logic ff / ir paf ef / or pae hf /( wxo ) read pointer read control logic write control logic write pointer expansion logic reset logic wen wclk d0-d17 ld rs ( hf )/ wxo wxi ren rclk oe q0-q17 rxo rxi fl 4294 drw 01 description: the idt72v205/72v215/72v225/72v235/72v245 are functionally com- patible versions of the idt72205lb/72215lb/72225lb/72235lb/72245lb, designed to run off a 3.3v supply for exceptionally low power consumption. these devices are very high-speed, low-power first-in, first-out (fifo) memories with clocked read and write controls. these fifos are applicable for a wide variety of data buffering needs, such as optical disk controllers, local area networks (lans), and interprocessor communication. these fifos have 18-bit input and output ports. the input port is controlled by a free-running clock (wclk), and an input enable pin ( wen ). data is read into the synchronous fifo on every clock when wen is asserted. the output port is controlled by another clock pin (rclk) and another enable pin ( ren ). the read clock(rclk) can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. an output enable pin ( oe ) is provided on the read port for three-state control of the output. the synchronous fifos have two fixed flags, empty flag/output ready ( ef / or ) and full flag/input ready ( ff / ir ), and two programmable flags, almost-empty ( pae ) and almost-full ( paf ). the offset loading of the program-
2 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges pin configurations tqfp (pn64-1, order code: pf) stqfp (pp64-1, order code: tf) top view description (continued) pin 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d 16 d 17 gnd rclk ren ld oe rs v cc gnd ef q 17 q 16 gnd q 15 v cc q 14 q 13 gnd q 12 q 11 v cc q 10 q 9 gnd q 8 q 7 q 6 q 5 gnd q 4 v cc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 pae fl wclk wen wxi v cc paf rxi ff wxo / hf rxo q 0 q 1 gnd q 2 q 3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4294 drw 02 mable flags is controlled by a simple state machine, and is initiated by asserting the load pin ( ld ). a half-full flag ( hf ) is available when the fifo is used in a single device configuration. there are two possible timing modes of operation with these devices: idt standard mode and first word fall-through (fwft) mode. in idt standard mode, the first word written to an empty fifo will not appear on the data output lines unless a specific read operation is performed. a read operation, which consists of activating ren and enabling a rising rclk edge, will shift the word from internal memory to the data output lines. in fwft mode, the first word written to an empty fifo is clocked directly to the data output lines after three transitions of the rclk signal. a ren does not have to be asserted for accessing the first word. these devices are depth expandable using a daisy-chain technique or first word fall through mode (fwft). the xi and xo pins are used to expand the fifos. in depth expansion configuration, first load ( fl ) is grounded on the first device and set to high for all other devices in the daisy chain. the idt72v205/72v215/72v225/72v235/72v245 are fabricated using idts high-speed submicron cmos technology.
3 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges pin description symbol name i/o description d0Cd17 data inputs i data inputs for an 18-bit bus. rs reset i when rs is set low, internal read and write pointers are set to the first location of the ram array, ff and paf go high, and pae and ef go low. a reset is required before an initial write after power-up. wclk write clock i when wen is low, data is written into the fifo on a low-to-high transition of wclk, if the fifo is not full. wen write enable i when wen is low, data is written into the fifo on every low-to-high transition of wclk. when wen is high, the fifo holds the previous data. data will not be written into the fifo if the ff is low. rclk read clock i when ren is low, data is read from the fifo on a low-to-high transition of rclk, if the fifo is not empty. ren read enable i when ren is low, data is read from the fifo on every low-to-high transition of rclk. when ren is high, the output register holds the previous data. data will not be read from the fifo if the ef is low. oe output enable i when oe is low, the data output bus is active. if oe is high, the output data bus will be in a high-impedance state. ld load i when ld is low, data on the inputs d0Cd11 is written to the offset and depth registers on the low-to-high transition of the wclk, when wen is low. when ld is low, data on the outputs q0Cq11 is read from the offset and depth registers on the low-to-high transition of the rclk, when ren is low. fl first load i in the single device or width expansion configuration, fl together with wxi and rxi determine if the mode is idt standard mode or first word fall through (fwft) mode, as well as whether the pae / paf flags are synchronous or asynchronous. (see table 1.) in the daisy chain depth expansion configuration, fl is grounded on the first device (first load device) and set to high for all other devices in the daisy chain. wxi write expansion i in the single device or width expansion configuration, wxi together with fl and rxi determine if the mode input is idt standard mode or fwft mode, as well as whether the pae / paf flags are synchronous or asynchronous. (see table 1.) in the daisy chain depth expansion configuration, wxi is connected to wxo (write expansion out) of the previous device. rxi read expansion i in the single device or width expansion configuration, rxi together with fl and wxi , determine if the mode input is idt standard mode or fwft mode, as well as whether the pae / paf flags are synchronous or asynchronous. (see table 1.) in the daisy chain depth expansion configuration, rxi is connected to rxo (read expansion out) of the previous device. ff / ir full flag/ o in the idt standard mode, the ff function is selected. ff indicates whether or not the fifo memory is full. in input ready the fwft mode, the ir function is selected. ir indicates whether or not there is space available for writing to the fifo memory. ef / or empty flag/ o in the idt standard mode, the ef function is selected. ef indicates whether or not the fifo memory is empty. output ready in fwft mode, the or function is selected. or indicates whether or not there is valid data available at the outputs. pae programmable o when pae is low, the fifo is almost-empty based on the offset programmed into the fifo. the default almost-empty flag offset at reset is 31 from empty for idt72v205, 63 from empty for idt72v215, and 127 from empty for idt72v225/ 72v235/72v245. paf programmable o when paf is low, the fifo is almost-full based on the offset programmed into the fifo. the default offset at almost-full flag reset is 31 from full for idt72v205, 63 from full for idt72v215, and 127 from full for idt72v225/72v235/72v245. wxo / hf write expansion o in the single device or width expansion configuration, the device is more than half full when hf is low. in the out/half-full flag depth expansion configuration, a pulse is sent from wxo to wxi of the next device when the last location in the fifo is written. rxo read expansion o in the depth expansion configuration, a pulse is sent from rxo to rxi of the next device when the last out location in the fifo is read. q0Cq17 data outputs o data outputs for an 18-bit bus. v cc power +3.3v power supply pins. gnd ground seven ground pins.
4 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges recommended dc operating conditions symbol parameter min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v commercial/industrial gnd supply voltage 0 0 0 v v ih input high voltage 2.0 5.5 v commercial/industrial v il (1) input low voltage -0.5 0.8 v commercial/industrial t a operating temperature 0 70 c commercial t a operating temperature -40 ? 85 c industrial note: 1. 1.5v undershoots are allowed for 10ns once per cycle. symbol rating commercial unit v term (2) terminal voltage C0.5 to +5 v with respect to gnd t stg storage C55 to +125 c temperature i out dc output current C50 to +50 ma symbol parameter (1) conditions max. unit c in (2) input v in = 0v 10 pf capacitance c out (1,2) output v out = 0v 10 pf capacitance capacitance (t a = +25 c, f = 1.0mhz) notes: 1. with output deselected, ( oe 3 v ih ). 2. characterized values, not currently tested. idt72v205 idt72v215 idt72v225 idt72v235 idt72v245 commercial & industrial (1) t clk = 10, 15, 20 ns symbol parameter min. typ. max. unit i li (2) input leakage current (any input) C1 1 a i lo (3) output leakage current C10 10 a v oh output logic 1 voltage, i oh = C2 ma 2.4 v v ol output logic 0 voltage, i ol = 8 ma 0.4 v i cc1 (4,5,6) active power supply current 30 ma i cc2 (4.7) standby current 5 ma dc electrical characteristics (commercial: v cc = 3.3v 0.3v, t a = 0 c to +70 c; industrial: v cc = 3.3v 0.3v, ta = -40 c to +85 c) notes: 1. industrial temperature range product for the 15ns speed grade is available as a standard device. 2. measurements with 0.4 v in v cc . 3. oe 3 v ih, 0.4 v out v cc . 4. tested with outputs disabled (i out = 0). 5. rclk and wclk toggle at 20 mhz and data inputs switch at 10 mhz. 6. typical i cc1 = 2.04 + 0.88*f s + 0.02*c l *f s (in ma). these equations are valid under the following conditions: v cc = 3.3v, t a = 25 c, f s = wclk frequency = rclk frequency (in mhz, using ttl levels), data switching at f s /2, c l = capacitive load (in pf). 7. all inputs = v cc - 0.2v or gnd + 0.2v, except rclk and wclk, which toggle at 20 mhz. absolute maximum ratings note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminal only.
5 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges ac electrical characteristics (commercial: vcc = 3.3v 0.3v, ta = 0c to +70c; industrial: vcc = 3.3v 0.3v, ta = -40c to +85c) commercial com'l & ind'l (1) commercial idt72v205l10 idt72v205l15 idt72v205l20 idt72v215l10 idt72v215l15 idt72v215l20 idt72v225l10 idt72v225l15 idt72v225l20 idt72v235l10 idt72v235l15 idt72v235l20 idt72v245l10 idt72v245l15 idt72v245l20 symbol parameter min. max. min. max. min. max. unit f s clock cycle frequency 100 66.7 50 m h z t a data access time 2 6.5 2 10 2 12 ns t clk clock cycle time 10 15 20 ns t clkh clock high time 4.5 6 8 ns t clkl clock low time 4.5 6 8 ns t ds data set-up time 3 4 5 ns t dh data hold time 0.5 1 1 ns t ens enable set-up time 3 4 5 ns t enh enable hold time 0.5 1 1 ns t rs reset pulse width (2) 10 15 20 ns t rss reset set-up time 8 10 12 ns t rsr reset recovery time 8 10 12 ns t rsf reset to flag and output time 15 15 20 ns t olz output enable to output in low-z (3) 000ns t oe output enable to output valid 6 3 8 3 10 ns t ohz output enable to output in high-z (3) 1638310ns t wff write clock to full flag 6.5 10 12 ns t ref read clock to empty flag 6.5 10 12 ns t pafa clock to asynchronous programmable almost-full flag 17 20 22 ns t pafs write clock to synchronous programmablealmost-full flag 8 10 12 ns t paea clock to asynchronous programmable almost-empty flag 17 20 22 ns t paes read clock to synchronous programmable almost-empty flag 8 10 12 ns t hf clock to half-full flag 17 20 22 ns t xo clock to expansion out 6.5 10 12 ns t xi expansion in pulse width 3 6.5 8 ns t xis expansion in set-up time 3 5 8 ns t skew1 skew time between read clock & write clock for ff / ir 568ns and ef / or t skew2 (4) skew time between read clock & write clock for pae 14 18 20 ns and paf input pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 1 ac test conditions figure 1. output load * includes jig and scope capacitances. 30pf* 330 w 3.3v 510 w d.u.t. 4294 drw 03 notes: 1. industrial temperature range product for the 15ns speed grade is available as a standard device. all other speed grades are available by special order. 2. pulse widths less than minimum values are not allowed. 3. values guaranteed by design, not currently tested. 4. t skew2 applies to synchronous pae and synchronous paf only.
6 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges functional description timing modes: idt standard vs first word fall through (fwft) mode the idt72v205/72v215/72v225/72v235/72v245 support two different timing modes of operation. the selection of which mode will operate is determined during configuration at reset ( rs ). during a rs operation, the first load ( fl ), read expansion input ( rxi ), and write expansion input ( wxi ) pins are used to select the timing mode per the truth table shown in table 3. in idt standard mode, the first word written to an empty fifo will not appear on the data output lines unless a specific read operation is performed. a read operation, which consists of activating read enable ( ren ) and enabling a rising read clock (rclk) edge, will shift the word from internal memory to the data output lines. in fwft mode, the first word written to an empty fifo is clocked directly to the data output lines after three transitions of the rclk signal. a ren does not have to be asserted for accessing the first word. various signals, both input and output signals operate differently depending on which timing mode is in effect. idt standard mode in this mode, the status flags, ff , paf , hf , pae , and ef operate in the manner outlined in table 1. to write data into to the fifo, write enable ( wen ) must be low. data presented to the data in lines will be clocked into the fifo on subsequent transitions of the write clock (wclk). after the first write is performed, the empty flag ( ef ) will go high. subsequent writes will continue to fill up the fifo. the programmable almost-empty flag ( pae ) will go high after n + 1 words have been loaded into the fifo, where n is the empty offset value. the default setting for this value is stated in the footnote of table 1. this parameter is also user programmable. see section on programmable flag offset loading. if one continued to write data into the fifo, and we assumed no read operations were taking place, the half-full flag ( hf ) would toggle to low once the 129th (72v205), 257th (72v215), 513th (72v225), 1,025th (72v235), and 2,049th (72v245) word respectively was written into the fifo. continuing to write data into the fifo will cause the programmable almost-full flag ( paf ) to go low. again, if no reads are performed, the paf will go low after (256-m) writes for the idt72v205, (512-m) writes for the idt72v215, (1,024-m) writes for the idt72v225, (2,048-m) writes for the idt72v235 and (4,096Cm) writes for the idt72v245. the offset m is the full offset value. this parameter is also user programmable. see section on programmable flag offset loading. if there is no full offset specified, the paf will be low when the device is 31 away from completely full for idt72v205, 63 away from completely full for idt72v215, and 127 away from completely full for the idt72v225/72v235/72v245. when the fifo is full, the full flag ( ff ) will go low, inhibiting further write operations. if no reads are performed after a reset, ff will go low after d writes to the fifo. d = 256 writes for the idt72v205, 512 for the idt72v215, 1,024 for the idt72v225, 2,048 for the idt72v235 and 4,096 for the idt72v245, respectively. if the fifo is full, the first read operation will cause ff to go high. subsequent read operations will cause paf and the half-full flag ( hf ) to go high at the conditions described in table 1. if further read operations occur, without write operations, the programmable almost-empty flag ( pae ) will go low when there are n words in the fifo, where n is the empty offset value. if there is no empty offset specified, the pae will be low when the device is 31 away from completely empty for idt72v205, 63 away from completely empty for idt72v215, and 127 away from completely empty for idt72v225/72v235/ 72v245. continuing read operations will cause the fifo to be empty. when the last word has been read from the fifo, the ef will go low inhibiting further read operations. ren is ignored when the fifo is empty. first word fall through mode (fwft) in this mode, the status flags, ir , paf , hf , pae, and or operate in the manner outlined in table 2. to write data into to the fifo, wen must be low. data presented to the data in lines will be clocked into the fifo on subsequent transitions of wclk. after the first write is performed, the output ready ( or ) flag will go low. subsequent writes will continue to fill up the fifo. pae will go high after n + 2 words have been loaded into the fifo, where n is the empty offset value. the default setting for this value is stated in the footnote of table 2. this parameter is also user programmable. see section on programmable flag offset loading. if one continued to write data into the fifo, and we assumed no read operations were taking place, the hf would toggle to low once the 130th (72v205), 258th (72v215), 514th (72v225), 1,026th (72v235), and 2,050th (72v245) word respectively was written into the fifo. continuing to write data into the fifo will cause the paf to go low. again, if no reads are performed, the paf will go low after (257-m) writes for the idt72v205, (513-m) writes for the idt72v215, (1,025-m) writes for the idt72v225, (2,049Cm) writes for the idt72v235 and (4,097Cm) writes for the idt72v245, where m is the full offset value. the default setting for this value is stated in the footnote of table 2. when the fifo is full, the input ready ( ir ) flag will go high, inhibiting further write operations. if no reads are performed after a reset, ir will go high after d writes to the fifo. d = 257 writes for the idt72v205, 513 for the idt72v215, 1,025 for the idt72v225, 2,049 for the idt72v235 and 4,097 for the idt72v245. note that the additional word in fwft mode is due to the capacity of the memory plus output register. if the fifo is full, the first read operation will cause the ir flag to go low. subsequent read operations will cause the paf and hf to go high at the conditions described in table 2. if further read operations occur, without write operations, the pae will go low when there are n + 1 words in the fifo, where n is the empty offset value. if there is no empty offset specified, the pae will be low when the device is 32 away from completely empty for idt72v205, 64 away from completely empty for idt72v215, and 128 away from completely empty for idt72v225/72v235/72v245. continuing read operations will cause the fifo to be empty. when the last word has been read from the fifo, or will go high inhibiting further read operations. ren is ignored when the fifo is empty. programmable flag loading full and empty flag offset values can be user programmable. the idt72v205/ 72v215/72v225/72v235/72v245 has internal registers for these offsets. default settings are stated in the footnotes of table 1 and table 2. offset values are loaded into the fifo using the data input lines d 0 -d 11 . to load the offset registers, the load ( ld ) pin and wen pin must be held low. data present on d 0 -d 11 will be transferred in to the empty offset register on the first low-to-high transition of wclk. by continuing to hold the ld and wen pin low, data present on d 0 -d 11 will be transferred into the full offset register on the next transition of the wclk. the third transition again writes to the empty offset register. writing all offset registers does not have to occur at one time. one or two offset registers can be written and then by bringing the ld pin high, the fifo is returned to normal read/write operation. when the ld pin and wen are again set low, the next offset register in sequence is written.
7 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges the contents of the offset registers can be read on the data output lines q 0 - q 11 when the ld pin is set low and ren is set low. data can then be read on the next low-to-high transition of rclk. the first transition of rclk will present the empty offset value to the data output lines. the next transition of rclk will present the full offset value. offset register content can be read out in the idt standard mode only. it cannot be read in the fwft mode. synchronous vs asynchronous programmable flag tim- ing selection the idt72v205/72v215/72v225/72v235/72v245 can be configured during the "configuration at reset" cycle described in table 3 with either asynchronous or synchronous timing for pae and paf flags. if asynchronous pae / paf configuration is selected (as per table 3), the pae is asserted low on the low-to-high transition of rclk. pae is reset to high on the low-to-high transition of wclk. similarly, the paf is asserted low on the low-to-high transition of wclk and paf is reset to high on the low-to-high transition of rclk. for detail timing diagrams, see figure 13 for asynchronous pae timing and figure 14 for asynchronous paf timing. if synchronous pae / paf configuration is selected , the pae is asserted and updated on the rising edge of rclk only and not wclk. similarly, paf is asserted and updated on the rising edge of wclk only and not rclk. for detail timing diagrams, see figure 22 for synchronous pae timing and figure 23 for synchronous paf timing. register-buffered flag output selection the idt72v205/72v215/72v225/72v235/72v245 can be configured during the "configuration at reset" cycle described in table 4 with single, double or triple register-buffered flag output signals. the various combinations avail- able are described in table 4 and table 5. in general, going from single to double or triple buffered flag outputs removes the possibility of metastable flag indications on boundary states (i.e, empty or full conditions). the trade-off is the addition of clock cycle delays for the respective flag to be asserted. not all combinations of register-buffered flag outputs are supported. register-buffered outputs apply to the empty flag and full flag only. partial flags are not effected. table 4 and table 5 summarize the options available. number of words in fifo idt72v205 idt72v215 idt72v225 idt72v235 idt72v245 ff paf hf pae ef 00 0 0 0hhhll 1 to n (1) 1 to n (1) 1 to n (1) 1 to n (1) 1 to n (1) hh h lh (n + 1) to 128 (n + 1) to 256 (n + 1) to 512 (n + 1) to 1,024 (n + 1) to 2,048 h h h h h 129 to (256-(m+1)) (2) 257 to (512-(m+1)) (2) 513 to (1,024-(m+1)) (2) 1,025 to (2,048-(m+1)) (2) 2,049 to (4,096-(m+1)) (2) hh l hh (256-m) to 255 (512-m) to 511 (1,024-m) to 1,023 (2,048-m) to 2,047 (4,096-m) to 4,095 h l l h h 256 512 1,024 2,048 4,096 l l l h h table 1 ? status flags for idt standard mode table 2 ? status flags for fwft mode number of words in fifo idt72v205 idt72v215 idt72v225 idt72v235 idt72v245 ir paf hf pae or 00 0 0 0lhhlh 1 to (n + 1) (1) 1 to (n + 1) (1) 1 to (n + 1) (1) 1 to (n + 1) (1) 1 to (n + 1) (1) lhh l l (n + 2) to 129 (n + 2) to 257 (n + 2) to 513 (n + 2) to 1,025 (n + 2) to 2,049 l h h h l 130 to (257-(m+1)) (2) 258 to (513-(m+1)) (2) 514 to (1,025-(m+1)) (2) 1,026 to (2,049-(m+1)) (2) 2,050 to (4,097-(m+1)) (2) lh lh l (257-m) to 256 (513-m) to 512 (1,025-m) to 1,024 (2,049-m) to 2,048 (4,097-m) to 4,096 lllhl 257 513 1,025 2,049 4,097 h l l h l notes: 1. n = empty offset (default values : idt72v205 n = 31, idt72v215 n = 63, idt72v225/72v235/72v245 n = 127) 2. m = full offset (default values : idt72v205 m = 31, idt72v215 m = 63, idt72v225/72v235/72v245 m = 127) notes: 1. n = empty offset (default values : idt72v205 n=31, idt72v215 n = 63, idt72v225/72v235/72v245 n = 127) 2. m = full offset (default values : idt72v205 m=31, idt72v215 m = 63, idt72v225/72v235/72v245 m = 127)
8 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges notes: 1. in a daisy-chain depth expansion, fl is held low for the "first load device". the rxi and wxi inputs are driven by the corresponding rxo and wxo outputs of the preceding device. 2. in a daisy-chain depth expansion, fl is held high for members of the expansion other than the "first load device". the rxi and wxi inputs are driven by the corresponding rxo and wxo outputs of the preceding device. table 3 ? truth table for configuration at reset fl rxi wxi ef / or ff / ir pae , paf fifo timing mode 0 0 0 single register-buffered single register-buffered asynchronous standard empty flag full flag 0 0 1 triple register-buffered double register-buffered asynchronous fwft output ready flag input ready flag 0 1 0 double register-buffered double register-buffered asynchronous standard empty flag full flag 0 (1) 1 1 single register-buffered single register-buffered asynchronous standard empty flag full flag 1 0 0 single register-buffered single register-buffered synchronous standard empty flag full flag 1 0 1 triple register-buffered double register-buffered synchronous fwft output ready flag input ready flag 1 1 0 double register-buffered double register-buffered synchronous standard empty flag full flag 1 (2) 1 1 single register-buffered single register-buffered synchronous standard empty flag full flag table 4 ? register-buffered flag output options ? idt standard mode empty flag ( ef ) full flag ( ff ) partial flags programming at reset flag timing buffered output buffered output timing mode fl rxi wxi diagrams single single asynch 0 0 0 figure 9, 10 single single sync 1 0 0 figure 9, 10 double double asynch 0 1 0 figure 24, 26 double double synch 1 1 0 figure 24, 26 table 5 ? register-buffered flag output options ? fwft mode output ready ( or ) input ready ( ir ) partial flags programming at reset flag timing fl rxi wxi diagrams triple double asynch 0 0 1 figure 27 triple double sync 1 0 1 figure 20, 21
9 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges figure 2. writing to offset registers ld wen wclk selection 0 0 writing to offset registers: empty offset full offset 0 1 no operation 1 0 write into fifo 1 1 no operation figure 3. offset register location and default values signal descriptions: inputs: data in (d 0 - d 17 ) data inputs for 18-bit wide data. controls: reset ( rs ) reset is accomplished whenever the reset ( rs ) input is taken to a low state. during reset, both internal read and write pointers are set to the first location. a reset is required after power-up before a write operation can take place. the half-full flag ( hf ) and programmable almost-full flag ( paf ) will be reset to high after t rsf . the programmable almost-empty flag ( pae ) will be reset to low after t rsf . the full flag ( ff ) will reset to high. the empty flag ( ef ) will reset to low in idt standard mode but will reset to high in fwft mode. during reset, the output register is initialized to all zeros and the offset registers are initialized to their default values. write clock (wclk) a write cycle is initiated on the low-to-high transition of the write clock (wclk). data setup and hold times must be met with respect to the low-to-high transition of wclk. the write and read clocks can be asynchronous or coincident. write enable ( wen ) when the wen input is low, data may be loaded into the fifo ram array on the rising edge of every wclk cycle if the device is not full. data is stored in the ram array sequentially and independently of any ongoing read operation. when wen is high, no new data is written in the ram array on each wclk cycle. to prevent data overflow in the idt standard mode, ff will go low, inhibiting further write operations. upon the completion of a valid read cycle, ff will go high allowing a write to occur. the ff flag is updated on the rising edge of wclk. to prevent data overflow in the fwft mode, ir will go high, inhibiting further write operations. upon the completion of a valid read cycle, ir will go low allowing a write to occur. the ir flag is updated on the rising edge of wclk. wen is ignored when the fifo is full in either fwft or idt standard mode. read clock (rclk) data can be read on the outputs on the low-to-high transition of the read clock (rclk), when output enable ( oe ) is set low. the write and read clocks can be asynchronous or coincident. read enable ( ren ) when read enable is low, data is loaded from the ram array into the output register on the rising edge of every rclk cycle if the device is not empty. when the ren input is high, the output register holds the previous data and no new data is loaded into the output register. the data outputs q 0 -q n maintain the previous data value. in the idt standard mode, every word accessed at q n , including the first word written to an empty fifo, must be requested using ren . when the last word has been read from the fifo, the empty flag ( ef ) will go low, inhibiting further read operations. ren is ignored when the fifo is empty. once a write is performed, ef will go high allowing a read to occur. the ef flag is updated on the rising edge of rclk. in the fwft mode, the first word written to an empty fifo automatically goes to the outputs q n , on the third valid low to high transition of rclk + t skew after the first write. ren does not need to be asserted low. in order to access all other words, a read must be executed using ren . the rclk low to high transition after the last word has been read from the fifo, output ready ( or ) will go high with a true read (rclk with ren = low), inhibiting further read operations. ren is ignored when the fifo is empty. output enable ( oe ) when output enable ( oe ) is enabled (low), the parallel output buffers receive data from the output register. when oe is disabled (high), the q output data bus is in a high-impedance state. load ( ld ) the idt72v205/72v215/72v225/72v235/72v245 devices contain two 12-bit offset registers with data on the inputs, or read on the outputs. when the load ( ld ) pin is set low and wen is set low, data on the inputs d0-d11 is written into the empty offset register on the first low-to-high transition of the write clock (wclk). when the ld pin and wen are held low then data is written into the full offset register on the second low-to-high transition of wclk. the third transition of wclk again writes to the empty offset register. however, writing all offset registers does not have to occur at one time. one or two offset registers can be written and then by bringing the ld pin high, the fifo is returned to normal read/write operation. when the ld pin is set low, and wen is low, the next offset register in sequence is written. empty offset register 17 11 0 001fh (72v205) 003fh (72v215): 007fh (72v225/72v235/72v245) full offset register 17 11 0 default value default value 001fh (72v205) 003fh (72v215): 007fh (72v225/72v235/72v245) 4294 drw 04 note: 1. any bits of the offset register not being programmed should be set to zero. note: 1. the same selection sequence applies to reading from the registers. ren is enabled and read is performed on the low-to-high transition of rclk.
10 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges when the ld pin is low and wen is high, the wclk input is disabled; then a signal at this input can neither increment the write offset register pointer, nor execute a write. the contents of the offset registers can be read on the output lines when the ld pin is set low and ren is set low; then, data can be read on the low- to-high transition of the read clock (rclk). the act of reading the control registers employs a dedicated read offset register pointer. (the read and write pointers operate independently). offset register content can be read out in the idt standard mode only. it is inhibited in the fwft mode. a read and a write should not be performed simultaneously to the offset registers. first load ( fl ) for the single device mode, see table 3 for additional information. in the daisy chain depth expansion configuration, fl is grounded to indicate it is the first device loaded and is set to high for all other devices in the daisy chain. (see operating configurations for further details.) write expansion input ( wxi ) this is a dual purpose pin. for single device mode, see table 3 for additional information. wxi is connected to write expansion out ( wxo ) of the previous device in the daisy chain depth expansion mode. read expansion input ( rxi ) this is a dual purpose pin. for single device mode, see table 3 for additional information. rxi is connected to read expansion out ( rxo ) of the previous device in the daisy chain depth expansion mode. outputs: full flag/input ready ( ff / ir ) this is a dual purpose pin. in idt standard mode, the full flag ( ff ) function is selected. when the fifo is full, ff will go low, inhibiting further write operations. when ff is high, the fifo is not full. if no reads are performed after a reset, ff will go low after d writes to the fifo. d = 256 writes for the idt72v205, 512 for the idt72v215, 1,024 for the idt72v225, 2,048 for the idt72v235 and 4,096 for the idt72v245. in fwft mode, the input ready ( ir ) function is selected. ir goes low when memory space is available for writing in data. when there is no longer any free space left, ir goes high, inhibiting further write operations. ir will go high after d writes to the fifo. d = 257 writes for the idt72v205, 513 for the idt72v215, 1,025 for the idt72v225, 2,049 for the idt72v235 and 4,097 for the idt72v245. note that the additional word in fwft mode is due to the capacity of the memory plus output register. ff / ir is synchronous and updated on the rising edge of wclk. empty flag/output ready ( ef / or ) this is a dual purpose pin. in the idt standard mode, the empty flag ( ef ) function is selected. when the fifo is empty, ef will go low, inhibiting further read operations. when ef is high, the fifo is not empty. in fwft mode, the output ready ( or ) function is selected. or goes low at the same time that the first word written to an empty fifo appears valid on the outputs. or stays low after the rclk low to high transition that shifts the last word from the fifo memory to the outputs. or goes high only with a true read (rclk with ren = low). the previous data stays at the outputs, indicating the last word was read. further data reads are inhibited until or goes low again. ef / or is synchronous and updated on the rising edge of rclk. programmable almost-full flag ( paf ) the programmable almost-full flag ( paf ) will go low when fifo reaches the almost-full condition. in idt standard mode, if no reads are performed after reset ( rs ), the paf will go low after (256-m) writes for the idt72v205, (512-m) writes for the idt72v215, (1,024-m) writes for the idt72v225, (2,048Cm) writes for the idt72v235 and (4,096Cm) writes for the idt72v245. the offset m is defined in the full offset register. in fwft mode, if no reads are performed, paf will go low after 257-m for the idt72v205, 513-m for the idt72v215, 1,025 for the idt72v225, 2,049 for the idt72v235 and 4,097 for the idt72v245. the default values for m are noted in table 1 and 2. if asynchronous paf configuration is selected, the paf is asserted low on the low-to-high transition of the write clock (wclk). paf is reset to high on the low-to-high transition of the read clock (rclk). if synchronous paf configuration is selected (see table 3), the paf is updated on the rising edge of wclk. programmable almost-empty flag ( pae ) the pae flag will go low when the fifo reaches the almost-empty condition. in idt standard mode, pae will go low when there are n words or less in the fifo. in fwft mode, the pae will go low when there are n + 1 words or less in the fifo. the offset "n" is defined as the empty offset. the default values for n are noted in table 1 and 2. if there is no empty offset specified, the programmable almost-empty flag ( pae ) will be low when the device is 31 away from completely empty for idt72v205, 63 away from completely empty for idt72v215, and 127 away from completely empty for idt72v225/72v235/72v245. if asynchronous pae configuration is selected, the pae is asserted low on the low-to-high transition of the read clock (rclk). pae is reset to high on the low-to-high transition of the write clock (wclk). if synchronous pae configuration is selected (see table 3), the pae is updated on the rising edge of rclk. write expansion out/half-full flag ( wxo / hf ) this is a dual-purpose output. in the single device and width expansion mode, when write expansion in ( wxi ) and/or read expansion in ( rxi ) are grounded, this output acts as an indication of a half-full memory. after half of the memory is filled, and at the low-to-high transition of the next write cycle, the half-full flag goes low and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. the half-full flag ( hf ) is then reset to high by the low-to-high transition of the read clock (rclk). the hf is asynchronous. in the daisy chain depth expansion mode, wxi is connected to wxo of the previous device. this output acts as a signal to the next device in the daisy chain by providing a pulse when the previous device writes to the last location of memory. read expansion out ( rxo ) in the daisy chain depth expansion configuration, read expansion in ( rxi ) is connected to read expansion out ( rxo ) of the previous device. this output acts as a signal to the next device in the daisy chain by providing a pulse when the previous device reads from the last location of memory. data outputs (q0-q17) q 0 -q 17 are data outputs for 18-bit wide data.
11 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges notes: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk edge. 2. select this mode by setting ( fl , rxi , wxi ) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset. figure 5. reset timing (2) figure 6. write cycle timing with single register-buffered ff (idt standard mode) wclk d 0 - d 17 wen ff t clk t clkh t clkl t ds t ens t dh t enh t wff t wff data in valid no operation rclk t skew1 (1) ren 4294 drw 06 rs ren , wen , ld pae paf , wxo / hf , rxo q 0 - q 17 oe = 0 oe = 1 (1) 4294 drw 05 t rss configuration setting t rsr fl , rxi , wxi rclk, wclk ff / ir ef / or fwft mode idt standard mode (3) (2) t rsf t rsf t rsf t rsf t rsf t rsr t rs fwft mode idt standard mode (4) notes: 1. single device mode ( fl , rxi , wxi ) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). fl , rxi , wxi should be static (tied to v cc or gnd). 2. the clocks (rclk, wclk) can be free-running asynchronously or coincidentally. 3. after reset, the outputs will be low if oe = 0 and tri-state if oe = 1. 4. in fwft mode ir goes low based on the wclk edge after reset.
12 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges figure 8. first data word latency with single register-buffered ef (idt standard mode) notes: 1. when t skew1 minimum specification, t frl (maximum) = t clk + t skew1 . when t skew1 < minimum specification, t frl (maximum) = either 2*t clk + t skew1 or t clk + t skew1 . the latency timing applies only at the empty boundary ( ef = low). 2. the first word is available the cycle after ef goes high, always. 3. select this mode by setting ( fl , rxi , wxi ) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset. figure 7. read cycle timing with single register-buffered ef (idt standard mode) notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high during the current clock cycle. if the time between the rising edge of wclk and the rising edge of rclk is less than t skew1 , then ef may not change state until the next rclk edge. 2. select this mode by setting ( fl , rxi , wxi ) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset. wclk d 0 - d 17 wen rclk ef q 0 - q 17 ren t ds t skew1 t ens t ref t a d 0 d 1 d 2 d 3 d 0 d 1 (first valid write) t oe t olz oe t a t frl (1) d 4 t ens 4294 drw 08 no operation rclk ren ef t clk t clkh t clkl t ens t enh t ref t ref valid data t a t olz t oe t ohz q 0 - q 17 oe wclk wen t skew1 (1) 4294 drw 07
13 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges figure 10. single register-buffered empty flag timing (idt standard mode) notes: 1. when t skew1 minimum specification, t frl (maximum) = t clk + t skew1. when t skew1 < minimum specification, t frl (maximum) = either 2 * t clk + t skew1, or t clk + t skew1. the latency timing apply only at the empty boundary ( ef = low). 2. select this mode by setting ( fl , rxi , wxi ) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset. notes: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk edge. 2. select this mode by setting ( fl , rxi , wxi ) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset. figure 9. single register-buffered full flag timing (idt standard mode) wclk d 0 - d 17 wen rclk ef q 0 - q 17 oe t ds t ens t a t skew1 data write 1 data read t enh t ref t ds t ens data write 2 t enh t ref ren data in output register t frl (1) low 4294 drw 10 t ref t skew1 t frl (1) data read wclk d 0 - d 17 wen rclk ff q 0 - q 17 t a t wff data write ren t wff t enh t ens t ds t wff t ds data write next data read t a no write no write data in output register oe low t skew1 (1) t skew1 (1) t enh t ens 4294 drw 09
14 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges figure 13. asynchronous programmable almost-empty flag timing (idt standard and fwft modes) figure 11. write programmable registers (idt standard and fwft modes) figure 12. read programmable registers (idt standard mode) notes: 1. n = pae offset. 2. for idt standard mode. 3. for fwft mode. 4. pae is asserted low on rclk transition and reset to high on wclk transition. 5. select this mode by setting ( fl , rxi , wxi ) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during reset. wclk t clkh t clkl t ens t enh wen pae t ens t paea n + 1 words in fifo (2) , n + 2 words in fifo (3) n words in fifo (2) , n + 1 words in fifo (3) rclk t paea ren 4294 drw 13 n words in fifo (2) , n + 1 words in fifo (3) rclk t clkh t clkl t clk t ens t enh ld ren q 0 - q 15 pae offset paf offset pae offset unknown t a t ens 4294 drw 12 wclk t clkh t clkl t clk t ens t enh ld wen d 0 - d 15 t ds t dh pae offset paf offset d 0 - d 11 pae offset t ens 4294 drw 11
15 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges notes: 1. d = maximum fifo depth. in idt standard mode: d = 256 for the idt72v205, 512 for the idt72v215, 1,024 for the idt72v225, 2,048 for the idt72v235 and 4 ,096 for the idt72v245. in fwft mode: d = 257 for the idt72v205, 513 for the idt72v215, 1,025 for the idt72v225, 2,049 for the idt72v235 and 4,097 for the idt72v245. 2. for idt standard mode. 3. for fwft mode. 4. select this mode by setting ( fl , rxi , wxi ) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset. figure 15. half-full flag timing (idt standard and fwft modes) figure 14. asynchronous programmable almost-full flag timing (idt standard and fwft modes) notes: 1. m = paf offset. 2. d = maximum fifo depth. in idt standard mode: d = 256 for the idt72v205, 512 for the idt72v215, 1,024 for the idt72v225, 2,048 for the idt72v235 and 4 ,096 for the idt72v245. in fwft mode: d = 257 for the idt72v205, 513 for the idt72v215, 1,025 for the idt72v225, 2,049 for the idt72v235 and 4,097 for the idt72v245. 3. paf is asserted to low on wclk transition and reset to high on rclk transition. 4. select this mode by setting ( fl , rxi , wxi ) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during reset. wclk t ens t enh wen hf t ens t hf rclk t hf ren 4294 drw 15 t clkl t clkh d/2 words in fifo (2) , [ + 1 ] words in fifo (3) d-1 2 d/2 + 1 words in fifo (2) , [ + 2 ] words in fifo (3) d-1 2 d/2 words in fifo (2) , [ + 1 ] words in fifo (3) d-1 2 wclk t clkh t clkl t ens t enh wen paf t ens t pafa d - (m + 1) words in fifo rclk t pafa ren (1) 4294 drw 14 d - m words in fifo d - (m + 1) words in fifo
16 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges figure 18. write expansion in timing figure 19. read expansion in timing note: 1. read from last physical location. figure 17. read expansion out timing note: 1. write to last physical location. figure 16. write expansion out timing rxi rclk t xi t xis 4294 drw 19 wxi wclk t xi t xis 4294 drw 18 rclk ren t ens rxo t clkh t xo note 1 t xo 4294 drw 17 wclk wen t ens wxo t clkh t xo note 1 t xo 4294 drw 16
17 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges figure 20. write timing with synchronous programmable flags (fwft mode) notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge for or to go low after two rclk cycles plus t ref . if the time between the rising edge of wlck and the rising edge of rclk is less than t skew1 , then the or deassertion may be delayed one extra rclk cycle. 2. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge for pae to go high during the current clock cycle. if the time between the rising edge of wclk and the rising edge of rclk is less tha n t skew2 , then the pae deassertion may be delayed one extra rclk cycle. 3. ld = high, oe = low 4. n = pae offset, m = paf offset, d = maximum fifo depth = 257 words for the idt72v205, 513 words for the idt72v215, 1,025 words for the idt72v225, 2,04 9 words for the idt72v235 and 4,097 words for the idt72v245. 5. select this mode by setting ( fl , rxi , wxi ) = (1,0,1) during reset. w 1 w 2 w 4 w [n +2] w [d-m-1] w [d-m-2] w [d-1] w d w [n+3] w [n+4] w [d-m] w [d-m+1] wclk wen d 0 - d 17 rclk t dh t ds t ens t skew1 ren q 0 - q 17 paf hf pae ir t ds t ds t ds t skew2 t a t ref or t paes t hf t pafs t wff w [d-m+2] w 1 t enh 4294 drw 20 data in output register (2) w 3 1 2 3 1 1 d-1 2 +1 ] [ w d-1 +2 ] [ w 2 d-1 +3 ] [ w 2
18 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges figure 21. read timing with synchronous programmable flags (fwft mode) notes: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ir will go low after one wclk plus t wff . if the time between the rising edge of rlck and the rising edge of wclk is less than t skew1 , then the ir assertion may be delayed an extra wclk cycle. 2. t skew2 is the minimum time between a rising rclk edge and a rising wclk edge for paf to go high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less th an t skew2 , then the paf deassertion time may be delayed an extra wclk cycle. 3. ld = high 4. n = pae offset, m = paf offset, d = maximum fifo depth = 257 words for the idt72v205, 513 words for the idt72v215, 1,025 words for the idt72v225, 2,04 9 words for idt72v235 and 4,097 words for idt72v245. 5. select this mode by setting ( fl , rxi , wxi ) = (1,0,1) during reset. wclk 12 wen d 0 - d 17 rclk t ens ren q 0 - q 17 paf hf pae ir or w 1 w 1 w 2 w 3 w m+2 w [m+3] t ohz t skew1 t enh t ds t dh t oe t a t a t a t pafs t wff t wff t ens oe t skew2 w d 4294 drw 21 t paes w [d-n] w [d-n-1] t a t a t hf t ref w [d-1] w d t a w [d-n+1] w [m+4] w [d-n+2] (1) (2) 1 t ens d-1 ] [ w d-1 ] [ w
19 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges figure 22. synchronous programmable almost-empty flag timing (idt standard and fwft modes) notes: 1. n = pae offset. 2. for idt standard mode. 3. for fwft mode. 4. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge for pae to go high during the current clock cycle. if the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then the pae deassertion may be delayed one extra rclk cycle. 5. pae is asserted and updated on the rising edge of rclk only. 6. select this mode by setting ( fl , rxi , wxi ) = (1,0,0), (1,0,1), or (1,1,0) during reset. notes: 1. m = paf offset. 2. d = maximum fifo depth. in idt standard mode: d = 256 for the idt72v205, 512 for the idt72v215, 1,024 for the idt72v225, 2,048 for the idt72v235 and 4 ,096 for the idt72v245. in fwft mode: d = 257 for the idt72v205, 513 for the idt72v215, 1,025 for the idt72v225, 2,049 for the idt72v235 and 4,097 for the idt72v245. 3. t skew2 is the minimum time between a rising rclk edge and a rising wclk edge for paf to go high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew2 , then the paf deassertion time may be delayed an extra wclk cycle. 4. paf is asserted and updated on the rising edge of wclk only. 5. select this mode by setting ( fl , rxi , wxi ) = (1,0,0), (1,0,1), or (1,1,0) during reset. figure 23. synchronous programmable almost-full flag timing (idt standard and fwft modes) wclk t enh t clkh t clkl wen paf rclk ren 4294 drw 23 t ens t enh t ens d-(m+1)wordsinfifo d - m words in fifo t pafs d-(m+1)words in fifo t pafs t skew2 (3) t pafs wclk t enh t clkh t clkl wen pae rclk ren 4294 drw 22 t ens t enh t ens n words in fifo (2) , n + 1words in fifo (3) n + 1 words in fifo (2) , n + 2 words in fifo (3) t skew2 t paes n words in fifo (2) , n + 1 words in fifo (3) (4) t paes
20 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges figure 25. write cycle timing with double register-buffered ff (idt standard mode) notes: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high after one wclk cycle plus t wff . if the time between the rising edge of rclk and the rising edge of wclk is less than tskew1, then the ff deassertion time may be delayed an extra wclk cycle. 2. ld = high. 3. select this mode by setting ( fl , rxi , wxi ) = (0,1,0) or (1,1,0) during reset. figure 24. double register-buffered full flag timing (idt standard mode) notes: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high after one wclk cycle plus t rff . if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 . then the ff deassertion may be delayed an extra wclk cycle. 2. ld = high. 3. select this mode by setting ( fl , rxi , wxi ) = (0,1,0) or (1,1,0) during reset. wclk d 0 - d 17 wen ff rclk ren t ds t wff t wff data in valid no operation (1) t skew1 4294 drw 25 t ens t dh t enh 1 2 t clkh t clkl t clk d 0 - d 17 wen rclk ff ren t enh t enh q 0 - q 17 data read next data read data in output register low oe t skew1 data write 4294 drw 24 wclk no write 1 2 1 2 t ds no write t wff t wff t wff t a t ens t ens t skew1 t ds t a wd (1) (1)
21 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges figure 27. or flag timing and first word fall through when fifo is empty (fwft mode) notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high after one rclk cycle plus t ref . if the time between the rising edge of wclk and the rising edge of rclk is less than t skew1 . then the ef deassertion may be delayed an extra rclk cycle. 2. ld = high 3. select this mode by setting ( fl , rxi , wxi ) = (0,1,0) or (1,1,0) during reset. figure 26. read cycle timing with double register-buffered ef (idt standard timing) notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge for or to go high during the current cycle. if the time between the rising edge of wlck and the rising edge of rclk is less than t skew1 , then the or deassertion may be delayed one extra rclk cycle. 2. ld = high, oe = low 3. select this mode by setting ( fl , rxi , wxi ) = (0,0,1) or (1,0,1) during reset. w 1 w 2 w 4 w [n +2] w [n+3] wclk wen d 0 - d 17 rclk t dh t ds t ens t skew1 ren q 0 - q 17 t ds t a t ref or w 1 data in output register (1) w 3 1 2 3 t enh t ref 4294 drw 27 no operation rclk ren ef t clkl t enh t ref last word t a t olz t oe q 0 - q 17 oe wclk wen 4294 drw 26 d 0 - d 17 t ens t ens t enh t ds t dh first word t ohz t clk 12 t ref t skew1 t clkh (1)
22 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges operating configurations single device configuration a single idt 72v205/72v215/72v225/72v235/72v245 may be used when the application requirements are for 256/512/1,024/2,048/4,096 words or less. these fifos are in a single device configuration when the first load ( fl ), write expansion in ( wxi ) and read expansion in ( rxi ) control inputs are configured as ( fl , rxi , wxi = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset (figure 28). figure 28. block diagram of single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 synchronous fifo note: 1. do not connect any output control signals directly together. figure 29. block diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36 synchronous fifo memory used in a width expansion configuration width expansion configuration word width may be increased simply by connecting together the control signals of multiple devices. status flags can be detected from any one device. the exceptions are the empty flag/output ready and full flag/input ready. because of variations in skew between rclk and wclk, it is possible for flag assertion and deassertion to vary by one cycle between fifos. to avoid problems the user must create composite flags by gating the empty flags/output ready of every fifo, and separately gating all full flags/input ready. figure 29 demonstrates a 36-word width by using two idt72v205/72v215/72v225/ 72v235/72v245s. any word width can be attained by adding additional idt72v205/72v215/72v225/72v235/72v245s. these fifos are in a single device configuration when the first load ( fl ), write expansion in ( wxi ) and read expansion in ( rxi ) control inputs are configured as ( fl , rxi , wxi = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset (figure 29). please see the application note an-83. write clock (wclk) write enable ( wen ) read clock (rclk) read enable ( ren ) load ( ld ) output enable ( oe ) data in (d) data out (q) full flag/input ready ( ff / ir ) programmable ( pae ) half full flag ( hf ) empty flag/output ready ( ef / or ) programmable ( paf ) reset ( rs ) 72v205 72v215 72v225 72v235 72v245 72v205 72v215 72v225 72v235 72v245 reset ( rs ) 36 36 18 18 18 18 ff / ir ef / or 4294 drw 29 fl wxi rxi fl wxi rxi ff / ir ef / or write clock (wclk) write enable ( wen ) read clock (rclk) read enable ( ren ) load ( ld ) output enable ( oe ) data in (d 0 - d 17 ) data out (q 0 - q 17 ) full flag/input ready ( ff / ir ) programmable ( pae ) half-full flag ( hf ) empty flag/output ready ( ef / or ) programmable ( paf ) reset ( rs ) idt 72v205 72v215 72v225 72v235 72v245 4294 drw 28 fl rxi wxi
23 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges figure 30. block diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 synchronous fifo memory with programmable flags used in depth expansion configuration load write clock write enable read clock read enable output enable data in data out reset idt 72v205 72v215 72v225 72v235 72v245 wxo wxi rxo rxi first load ( fl ) fl vcc vcc wxo wxi rxo rxi wxo wxi rxo rxi idt 72v205 72v215 72v225 72v235 72v245 idt 72v205 72v215 72v225 72v235 72v245 ff / ir paf ef / or pae ff / ir paf ef / or pae ff / ir paf ef / or pae ef / or pae ff / ir paf 4294 drw 30 rclk ren oe wclk wen rs fl rclk ren oe wclk wen rs rclk ren oe wclk wen rs ld ld dn qn dn qn dn qn ld depth expansion configuration daisy chain technique (with programmable flags) these devices can easily be adapted to applications requiring more than 256/512/1,024/2,048/4,096 words of buffering. figure 30 shows depth expansion using three idt72v205/72v215/72v225/72v235/72v245s. maximum depth is limited only by signal loading. follow these steps: 1. the first device must be designated by grounding the first load ( fl ) control input. 2. all other devices must have fl in the high state. 3. the write expansion out ( wxo ) pin of each device must be tied to the write expansion in ( wxi ) pin of the next device. see figure 30. 4. the read expansion out ( rxo ) pin of each device must be tied to the read expansion in ( rxi ) pin of the next device. see figure 30. 5. all load ( ld ) pins are tied together. 6. the half-full flag ( hf ) is not available in this depth expansion configuration. 7. ef , ff , pae , and paf are created with composite flags by oring together every respective flags for monitoring. the composite pae and paf flags are not precise. 8. in daisy chain mode, the flag outputs are single register-buffered and the partial flags are in asynchronous timing mode.
24 idt72v205/72v215/72v225/72v235/72v245 3.3v cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges figure 31. block diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 synchronous fifo memory with programmable flags used in depth expansion configuration dn input ready write enable write clock wen wclk ir data in rclk read clock rclk ren oe output enable output ready qn dn ir gnd wen wclk or ren oe qn read enable or data out transfer clock 4294 drw 31 n n rxi hf 72v205 72v215 72v225 72v235 72v245 wxi fl v cc gnd (0,1) 72v205 72v215 72v225 72v235 72v245 rxi wxi fl v cc gnd (0,1) paf hf pae n depth expansion configuration (fwft mode) in fwft mode, the fifos can be connected in series (the data outputs of one fifo connected to the data inputs of the next) with no external logic necessary. the resulting configuration provides a total depth equivalent to the sum of the depths associated with each single fifo. figure 31 shows a depth expansion using two idt72v205/72v215/72v225/72v235/72v245 devices. care should be taken to select fwft mode during master reset for all fifos in the depth expansion configuration. the first word written to an empty configuration will pass from one fifo to the next (ripple down) until it finally appears at the outputs of the last fifo in the chainCno read operation is necessary but the rclk of each fifo must be free-running. each time the data word appears at the outputs of one fifo, that devices or line goes low, enabling a write to the next fifo in line. for an empty expansion configuration, the amount of time it takes for or of the last fifo in the chain to go low (i.e. valid data to appear on the last fifos outputs) after a word has been written to the first fifo is the sum of the delays for each individual fifo: (n C 1)*(4*transfer clock) + 3*t rclk where n is the number of fifos in the expansion and t rclk is the rclk period. note that extra cycles should be added for the possibility that the t skew1 specification is not met between wclk and transfer clock, or rclk and transfer clock, for the or flag. the ripple down delay is only noticeable for the first word written to an empty depth expansion configuration. there will be no delay evident for subsequent words written to the configuration. the first free location created by reading from a full depth expansion configuration will bubble up from the last fifo to the previous one until it finally moves into the first fifo of the chain. each time a free location is created in one fifo of the chain, that fifos ir line goes low, enabling the preceding fifo to write a word to fill it. for a full expansion configuration, the amount of time it takes for ir of the first fifo in the chain to go low after a word has been read from the last fifo is the sum of the delays for each individual fifo: (n C 1)*(3*transfer clock) + 2 t wclk where n is the number of fifos in the expansion and t wclk is the wclk period. note that extra cycles should be added for the possibility that the t skew1 specification is not met between rclk and transfer clock, or wclk and transfer clock, for the ir flag. the transfer clock line should be tied to either wclk or rclk, whichever is faster. both these actions result in data moving, as quickly as possible, to the end of the chain and free locations to the beginning of the chain.
25 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 (408) 330-1753 santa clara, ca 95054 fax: 408-492-8674 fifohelp@idt.com www.idt.com datasheet document history 05/02/2001 pgs. 4, 5 and 25. 01/11/2002 pg. 4. 02/01/2002 pg. 4. idt xxxxx device type x power xx speed x package x blank clock cycle time (t clk ) speed in nanoseconds process / temperature range 4294 drw 32 commercial only commercial (0 c to +70 c) industrial (-40 c to +85 c) i (1) pf tf thin plastic quad flatpack (tqfp, pn64-1) slim thin plastic quad flatpack (stqfp, pp64-1) 10 15 20 com'l & ind'l commercial only l low power 72v205 72v215 72v225 72v235 72v245 256 x 18 ? 3.3v syncfifo 512 x 18 ? 3.3v syncfifo 1,024 x 18 ? 3.3v syncfifo 2,048 x 18 ? 3.3v syncfifo 4,096 x 18 ? 3.3v syncfifo notes: 1. industrial temperature range product for the 15ns speed grade is available as a standard device. all other speed grades are available by special order. ordering information

▲Up To Search▲

Price & Availability of IDT72V235L20PFI

	To Download IDT72V235L20PFI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .